J.P. Morgan Analyzes TSMC: CoWoS Gap Expands to 20%, AI CPUs Take Over from GPUs

TL;DR
· J.P. Morgan's supply chain check raises TSMC's CoWoS forecast, expecting a monthly capacity of about 220,000 units by the end of 2028.
· NVIDIA, AMD, and cloud vendors' self-developed chips are competing for advanced packaging, with a gap of around 20% expected from 2027 to 2028.
· Related shipments, packaging routes, and customer allocations are largely model assumptions, and the yield rates for CoPoS, EMIB-T, and outsourced testing remain uncertain.

J.P. Morgan's latest supply chain check continues to raise TSMC's CoWoS capacity forecast, but the core judgment it provides is not that "the shortage is ending soon," but rather that "capacity is expanding rapidly, and demand is growing even faster." In the institution's model, the supply-demand gap for advanced packaging from 2027 to 2028 may still remain around 20%.

This is important because AI chips cannot simply be delivered by producing GPUs. High-end GPUs, AI CPUs, ASICs, and HBM need to be interconnected at high speeds within the same package, and CoWoS is one of the most critical advanced packaging solutions. Many AI hardware from companies like NVIDIA, AMD, Google, and Amazon cannot bypass this link.

TSMC's official materials have confirmed that the company continues to expand its CoWoS, SoIC, and other advanced packaging capacities, stating that CoWoS capacity is expected to grow at a compound annual growth rate of over 80% from 2022 to 2027. However, the monthly capacity, customer allocations, yield rates, and gap ratios have not been disclosed by TSMC, and the market currently relies more on brokerage supply chain checks and third-party estimates.

Capacity Raised to About 220,000 Units, Why Is It Still Not Enough

The most direct figure from this J.P. Morgan supply chain check is TSMC's own CoWoS monthly capacity forecast: about 115,000 units by the end of 2026, around 190,000 units in 2027, and approximately 220,000 to 225,000 units by the end of 2028.

Public second-hand reports vary slightly. Some reports indicate that J.P. Morgan's previous forecast for the end of 2027 was 175,000 units per month, and about 220,000 units per month by the end of 2028. Considering that these figures are not officially disclosed by TSMC, they are better understood as "upward-looking" scenarios in the supply chain model rather than confirmed capacity commitments.

Outsourced testing factories are also filling the gap. The CoWoS-like capacity of OSATs such as Amkor and ASE is expected to rise from about 12,000 to 15,000 units per month by the end of 2026 to about 85,000 units per month by the end of 2028. TSMC's internal resources are also shifting towards CoWoS, with some capacity originally planned for SoIC being redirected to support CoWoS.

CoWoS Capacity Expansion Trend: TSMC's monthly capacity is expected to rise from about 115,000 units in 2026 to about 220,000 to 225,000 units in 2028, with non-TSMC capacity also being adjusted upward.

However, the problem is that the consumption of packaging by AI chips is also increasing. High-end AI accelerators, AI CPUs, and custom ASICs are all increasing their packaging usage, with some chip designs having larger areas, requiring more wafers and packaging resources per product. In other words, while production lines are expanding, the capacity consumed by each chip is also increasing.

This approximately 20% gap judgment is not a market consensus. TrendForce stated in June that the CoWoS supply-demand gap might narrow from 20% to about 10% by the end of 2026, estimating TSMC's monthly capacity to be between 120,000 and 140,000 units, with OSATs adding 50,000 to 60,000 units per month. The differences in these judgments mainly arise from varying assumptions about the speed of demand growth and whether external capacity can smoothly translate into usable supply.

NVIDIA Remains the Largest Customer, CPUs Also Start Joining the Queue

In J.P. Morgan's model, NVIDIA remains the largest source of CoWoS demand. By 2028, NVIDIA's annual CoWoS demand is expected to reach about 1.735 million units, continuing to grow significantly compared to 2027.

This demand comes not only from the next generation of GPUs but also includes AI CPUs such as Vera and Rosa, LPUs, and products like Spectrum-X CPO. In the model assumptions, NVIDIA's accelerators and CPO products mainly use CoWoS-L, while CPUs and LPUs use more CoWoS-R, shared by TSMC, Amkor, and ASE.

This is a key change. In the past discussions about AI servers, people were more likely to think of "GPU plus HBM"; now, the CPU side also requires higher memory bandwidth, more complex interconnections, and higher system efficiency, so AI CPUs themselves will also consume advanced packaging capacity.

The design related to Feynman has not yet been fully determined. The current supply chain model does not explicitly state that it has adopted CoPoS; in the short term, it is more likely to still rely on CoWoS-L combined with some SoIC logic stacking. Even if new packaging routes emerge in the future, the main AI products from 2027 to 2028 will still find it difficult to bypass CoWoS.

AMD, TPU, and Trainium Compete Together, Shortage Not Just Belongs to NVIDIA

Focusing only on NVIDIA would underestimate the scope of this advanced packaging tension. AMD, Google TPU, and Amazon Trainium are also increasing their demand for CoWoS or similar advanced packaging.

AMD's pressure comes from both server CPUs and AI accelerators. Products like the Venice server CPU, MI450, and MI500 all require more advanced packaging resources in the model, with the MI500 having a larger packaging size, consuming more wafers and packaging capacity per unit product. AMD's overall demand for wafer-level fan-out is expected to continue rising from 2027 to 2028, but the actual fulfillment rate may only be 50% to 60%.

Google TPU is also adjusting upward. The total shipment forecast for TPU in 2027 has been raised, with the v8 series, in which MediaTek participates, contributing the main increment, and the v9 product cycle expected to enter in 2028. Some subsequent TPU projects may shift to Intel EMIB-T packaging, but this alternative route is still limited by substrate supply and yield rates.

Amazon Trainium is also accelerating. The lifecycle demand for Trainium3 has been raised, and some orders may overflow to Marvell. Trainium4 is expected to ramp up in 2028, introducing 3D SoIC logic stacking and various interconnection schemes. Related shipments and packaging routes remain model assumptions, ultimately depending on customer design decisions and mass production rhythms.

This explains why, after TSMC raised its advanced packaging capacity, the market still worries it won't be enough. Demand is no longer concentrated solely on NVIDIA GPUs; cloud vendors' self-developed chips, AI CPUs, and more complex packaging structures are all pushing up capacity consumption together.

Target Price of 3100 TWD, Betting on Continued Tightness in Packaging

J.P. Morgan maintains TSMC's "overweight" rating and sets a target price of 3100 TWD for June 2027, corresponding to about 20 times the forward P/E ratio for 12 months. The institution also raised its growth rate assumptions for TSMC's data center AI business, expecting a compound annual growth rate of about 69% from 2024 to 2029.

This target price is supported not only by the rising prices of CoWoS but also by the combined increase in advanced processes, packaging capacity, and AI customer orders, which enhance revenue visibility. From 2026 to 2028, TSMC's overall CoWoS consumption is expected to reach approximately 1.24 million, 2.38 million, and 2.63 million units per year, with NVIDIA maintaining the largest share and AMD and Broadcom/TPU contributing more increments.

Evolution of CoWoS Customer Composition: Total consumption is expected to rise from about 134,000 units per year in 2023 to about 2.38 million units per year in 2027, with NVIDIA still holding a major share.

However, this set of valuation numbers is not the most critical part to amplify. A more direct signal is that the expansion of AI infrastructure is pushing TSMC's advanced packaging to a supply bottleneck position. For high-end AI chip companies, securing advanced process capacity is not enough; whether they can secure sufficient CoWoS may also determine the delivery rhythm.

Alternative Routes Have Not Yet Stabilized, Uncertainties Remain After 2028

This round of adjustments still has clear boundaries: many numbers come from model assumptions and do not equate to confirmed occurrences.

CoPoS is still in the engineering debugging stage. The current timeline points to risk production in early 2028 and mass production in 2029, but risk production does not mean that customer products will be ramped up on schedule. Whether NVIDIA's Feynman and other future products will adopt CoPoS still depends on final design choices.

Caption: TSMC's SoIC capacity is expected to accelerate significantly by 2028.

OSAT expansion is also not a one-to-one replacement. Outsourced testing factories can share part of the CoWoS-like capacity, but substrate yield rates, customer certifications, equipment availability, and capacity priorities will all affect the actual usable amount. The fulfillment rate assumptions for customers like AMD are relatively low, indicating that external capacity cannot immediately fill the gap.

Intel EMIB-T is another potential alternative solution. Third-party estimates suggest that EMIB-T costs may be lower than CoWoS-L, and some TPU projects may consider shifting to this route. However, whether the cost advantage can be realized still depends on substrate supply, yield rates, and large-scale mass production experience.

Therefore, the real conclusion of this supply chain check is not that "TSMC's capacity expansion is fast enough," but rather that AI chips are becoming larger, more complex, and more diverse. TSMC and outsourced testing factories are both accelerating capacity expansion, but until CoPoS, EMIB-T, and OSAT capacities stabilize and ramp up, advanced packaging may still hinder the delivery of high-end AI hardware from 2027 to 2028.